Skill

sim-tool-profiles

Defines simulation tool profiles (Verilator, Iverilog, VCS, Xrun, Questa) with standardized run and replay commands, plus UVM coverage collection guidance.

automation

developer-tools

npx claudepluginhub babyworm/rtl-agent-team --plugin rtl-agent-team

Popularity

Stars

Forks

Invocation

How this skill is triggered — by the user, by Claude, or both

Slash command

/rtl-agent-team:sim-tool-profiles

Not user invocable

Model invocable

Inline context

Default effort

Context Preview

The summary Claude sees in its skill listing — used to decide when to auto-load this skill

- Prefer wrapper: `scripts/run_sim.sh`

SKILL.md

53 lines · ~541 tokens

Similar Skills

rtl-p5s-uvm-verify

Runs UVM-based verification on RTL using commercial simulators (VCS, Questa, Xcelium). Outputs test summaries and coverage reports.

5 files7 tools

rtl-agent-team

gf-sim

Simulates SystemVerilog designs using Verilator. Auto-detects DUT and testbench files, compiles with trace, runs simulation, and outputs structured PASS/FAIL results.

4 tools

gateflow

receiving-code-review

218.5k

Guides technical evaluation of code review feedback: read fully, restate for understanding, verify against codebase, respond with reasoning or pushback before implementing.

superpowers

Stats

LanguagePython

Stars23

Forks6

MaintenanceExcellent

Last CommitMay 26, 2026

Actions

View Source View Plugin View on GitHub View README

Help us improve

Share bugs, ideas, or general feedback.

Stats

Actions

Help us improve

Share bugs, ideas, or general feedback.

Simulation Tool Profiles

Common Contract

Prefer wrapper: scripts/run_sim.sh

Every run must emit:

primary log path
replay script path
pass/fail summary

Open-Source Baseline

verilator:

scripts/run_sim.sh --sim verilator --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports --trace

iverilog:

scripts/run_sim.sh --sim iverilog --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports

Commercial Profiles

vcs:

scripts/run_sim.sh --sim vcs --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports

xrun:

scripts/run_sim.sh --sim xrun --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports

questa:

scripts/run_sim.sh --sim questa --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports

UVM Coverage Collection (Commercial Only)

Code coverage must be enabled at both compile and runtime for all commercial simulators.

Simulator

Compile Flag

Runtime Flag

Coverage DB

Merge Tool

VCS

-cm line+cond+fsm+tgl+branch

-cm line+cond+fsm+tgl+branch -cm_dir <dir>.vdb

.vdb directory

urg -dir *.vdb -format both

Xcelium

-coverage all

-coverage all -covworkdir <dir>/cov_work -covscope tb_top

cov_work/ directory

imc -exec merge.tcl

Questa

+cover=bcestf (at vlog)

-coverage (at vsim) + -do "coverage save -onexit <file>.ucdb"

.ucdb file

vcover merge out.ucdb *.ucdb

Questa gotcha: +cover=bcestf at vlog compile is mandatory — runtime -coverage alone collects nothing.

UVM regression runner: skills/rtl-p5s-uvm-verify/scripts/run_regression_uvm.sh

Handles compile-once + parallel multi-seed execution + coverage merge per simulator

Targets: line ≥ 90%, toggle ≥ 80%, FSM ≥ 70%, branch ≥ 80%, functional ≥ 95%

Normalized Result Fields

tool

status (pass or fail)

errors_count

warnings_count

log_path

replay_path

Simulation Tool Profiles

Common Contract

Prefer wrapper: scripts/run_sim.sh
Every run must emit:
- primary log path
- replay script path
- pass/fail summary

Open-Source Baseline

verilator:
- scripts/run_sim.sh --sim verilator --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports --trace
iverilog:
- scripts/run_sim.sh --sim iverilog --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports

Commercial Profiles

vcs:
- scripts/run_sim.sh --sim vcs --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports
xrun:
- scripts/run_sim.sh --sim xrun --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports
questa:
- scripts/run_sim.sh --sim questa --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports

UVM Coverage Collection (Commercial Only)

Code coverage must be enabled at both compile and runtime for all commercial simulators.

Simulator	Compile Flag	Runtime Flag	Coverage DB	Merge Tool
VCS	`-cm line+cond+fsm+tgl+branch`	`-cm line+cond+fsm+tgl+branch -cm_dir <dir>.vdb`	`.vdb` directory	`urg -dir *.vdb -format both`
Xcelium	`-coverage all`	`-coverage all -covworkdir <dir>/cov_work -covscope tb_top`	`cov_work/` directory	`imc -exec merge.tcl`
Questa	`+cover=bcestf` (at `vlog`)	`-coverage` (at `vsim`) + `-do "coverage save -onexit <file>.ucdb"`	`.ucdb` file	`vcover merge out.ucdb *.ucdb`

Questa gotcha: +cover=bcestf at vlog compile is mandatory — runtime -coverage alone collects nothing.

UVM regression runner: skills/rtl-p5s-uvm-verify/scripts/run_regression_uvm.sh

Handles compile-once + parallel multi-seed execution + coverage merge per simulator
Targets: line ≥ 90%, toggle ≥ 80%, FSM ≥ 70%, branch ≥ 80%, functional ≥ 95%

Normalized Result Fields

tool
status (pass or fail)
errors_count
warnings_count
log_path
replay_path

sim-tool-profiles

Popularity

Invocation

Context Preview

SKILL.md

Similar Skills

Help us improve

Help us improve

Find plugins for your project

sim-tool-profiles

Popularity

Invocation

Context Preview

SKILL.md

Simulation Tool Profiles

Common Contract

Open-Source Baseline

Commercial Profiles

UVM Coverage Collection (Commercial Only)

Normalized Result Fields

Similar Skills

Help us improve

Simulation Tool Profiles

Common Contract

Open-Source Baseline

Commercial Profiles

UVM Coverage Collection (Commercial Only)

Normalized Result Fields