npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowThis skill is limited to using the following tools:
Compile and run SystemVerilog simulation with structured output.
Generates design tokens/docs from CSS/Tailwind/styled-components codebases, audits visual consistency across 10 dimensions, detects AI slop in UI.
Records polished WebM UI demo videos of web apps using Playwright with cursor overlay, natural pacing, and three-phase scripting. Activates for demo, walkthrough, screen recording, or tutorial requests.
Delivers idiomatic Kotlin patterns for null safety, immutability, sealed classes, coroutines, Flows, extensions, DSL builders, and Gradle DSL. Use when writing, reviewing, refactoring, or designing Kotlin code.
Compile and run SystemVerilog simulation with structured output.
Before running simulation, check if Verilator is available:
which verilator
If Verilator is not available, return immediately:
---GATEFLOW-RESULT---
STATUS: ERROR
ERRORS: 0
WARNINGS: 0
FILES: []
DETAILS: Simulation requires Verilator. Install it to enable simulation.
macOS: brew install verilator
Linux: sudo apt install verilator
---END-GATEFLOW-RESULT---
Do NOT attempt to simulate without Verilator. Return the ERROR status and let the orchestrator handle it.
If files specified in args: Use provided paths. First file is typically the testbench.
If no files specified: Auto-detect by scanning for SV files:
ls *.sv rtl/*.sv tb/*.sv 2>/dev/null
Testbench indicators (has any of):
initial begin$display, $monitor$finish, $fatal$dumpfile, $dumpvarsalways #N clk = ~clktb/ directory or named *_tb.sv, tb_*.svDUT indicators (has any of):
always_ff, always_comb$ system tasks (except assertions)rtl/ directoryQuick classification:
# Files with testbench markers
grep -l '\$display\|\$finish\|initial begin' *.sv 2>/dev/null
# Files with DUT markers
grep -l 'always_ff\|always_comb' *.sv 2>/dev/null
verilator --binary -j 0 -Wall --trace <dut-files> <testbench> -o sim
Notes:
--trace enables VCD waveform generation-o sim names the output executableIf multiple top modules detected:
verilator --binary -j 0 -Wall --trace --top-module <tb_name> <files> -o sim
./obj_dir/sim
Or if named differently:
./obj_dir/V<top_module>
Check output for:
PASS, SUCCESS, All tests passed -> PASSFAIL, ERROR, MISMATCH, ASSERT -> FAIL$fatal or non-zero exit code -> FAIL$finish reached without errors -> PASSCheck exit code:
./obj_dir/sim
echo "Exit code: $?"
ALWAYS end your response with this exact block format:
---GATEFLOW-RESULT---
STATUS: PASS|FAIL|ERROR
ERRORS: <count>
WARNINGS: <count>
FILES: <comma-separated list>
DETAILS: <one-line summary>
---END-GATEFLOW-RESULT---
Status definitions:
PASS: Simulation completed, tests passedFAIL: Simulation failed (compile error, assertion failure, test failure)ERROR: Could not run simulation (missing files, setup error)## File Classification
| File | Type | Reason |
|------|------|--------|
| rtl/fifo.sv | DUT | has always_ff, no $display |
| tb/tb_fifo.sv | TB | has $display, $finish, initial |
## Compilation
$ verilator --binary -j 0 -Wall --trace rtl/fifo.sv tb/tb_fifo.sv -o sim
(compilation output...)
## Simulation
$ ./obj_dir/sim
Test 1: Write single item... PASS
Test 2: Fill FIFO... PASS
Test 3: Overflow check... PASS
All tests passed!
---GATEFLOW-RESULT---
STATUS: PASS
ERRORS: 0
WARNINGS: 0
FILES: rtl/fifo.sv,tb/tb_fifo.sv
DETAILS: All 3 tests passed
---END-GATEFLOW-RESULT---
## Simulation
$ ./obj_dir/sim
Test 1: Write single item... PASS
Test 2: Read back... FAIL
Expected: 0xAB
Got: 0x00
$fatal called at tb_fifo.sv:87
---GATEFLOW-RESULT---
STATUS: FAIL
ERRORS: 1
WARNINGS: 0
FILES: rtl/fifo.sv,tb/tb_fifo.sv
DETAILS: Test 2 failed - read data mismatch at line 87
---END-GATEFLOW-RESULT---
$ verilator --binary -j 0 -Wall rtl/fifo.sv tb/tb_fifo.sv -o sim
%Error: rtl/fifo.sv:45: Cannot find: fifo_mem
---GATEFLOW-RESULT---
STATUS: FAIL
ERRORS: 1
WARNINGS: 0
FILES: rtl/fifo.sv,tb/tb_fifo.sv
DETAILS: Compile error - undefined reference to fifo_mem
---END-GATEFLOW-RESULT---
| Issue | Symptom | Solution |
|---|---|---|
| Multiple tops | "Multiple top modules" | Add --top-module <name> |
| Missing module | "Cannot find: X" | Include file defining X |
| X-values | Output shows X | Check reset coverage |
| Timeout | Simulation hangs | Add timeout or fix FSM |
| No $finish | Runs forever | Ensure TB calls $finish |
The /gf skill uses this skill internally and parses the result block:
Parse ---GATEFLOW-RESULT--- block:
- STATUS: PASS -> report success, done
- STATUS: FAIL -> spawn sv-debug agent with failure context
- STATUS: ERROR -> report setup issue to user