gateflow

Audit plugin quality and optionally auto-fix issues

List supported boards and query pinouts

Generate Python testbench using Cocotb

One-command demo - generates, lints, and simulates a working project

Scan codebase for missing IP blocks, stubs, and CDC issues

Plugin quality auditor — scans the entire GateFlow plugin for gaps, inconsistencies, missing features, stale content, and improvement opportunities. Produces a prioritized report with actionable fixes. Example: "audit the plugin", "what's missing", "find gaps in GateFlow"

Plugin hole-plugger — takes audit findings and automatically fixes gaps, stubs, inconsistencies, and missing content across the plugin. Works as a sub-agent that receives issues and implements fixes. Example: "fix all plugin gaps", "plug the holes", "auto-fix audit findings"

KiCad schematic and PCB generation specialist. Creates AI-verified draft schematics and PCB layouts with self-improving verification loop. Example requests: "design a breakout board for iCE40", "create schematic for FPGA dev board"

SystemVerilog RTL architect - Creates synthesizable modules and hardware blocks. This agent should be used when the user wants to create new SystemVerilog modules, implement FSMs, FIFOs, arbiters, pipelines, or any RTL design from scratch. Example requests: "create a FIFO module", "write an FSM for UART", "generate a round-robin arbiter"

RTL debug specialist - Diagnoses simulation failures and unexpected behavior. This agent should be used when the user has simulation issues, X-value propagation, timing problems, or code that doesn't work as expected. Example requests: "why is my output X", "simulation is stuck", "debug this failure"

Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hierarchy"

Parallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates. Example: "/gf-build RISC-V CPU with ALU, regfile, decoder, control FSM"

Python-based testbench generation using Cocotb. Alternative to SystemVerilog testbenches for Python-native hardware engineers. Example: "create a cocotb test for the FIFO", "write Python testbench"

Error translation layer for hardware tool outputs. Converts cryptic Verilator, Yosys, GHDL, and simulation errors into 3-layer explanations. Used internally by gf orchestrator — not user-invocable directly.

Expand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context.

6 hooks across 5 events