gateflow

Audit plugin quality and optionally auto-fix issues

List supported boards and query pinouts

Generate Python testbench using Cocotb

One-command demo - generates, lints, and simulates a working project

Scan codebase for missing IP blocks, stubs, and CDC issues

Env check

Fix lint

Flash bitstream to FPGA board

Run formal verification

Generate FuseSoC .core file for the project

Generate scaffolds

Manage IP block library

Run lint

Map codebase

Generate KiCad schematic and PCB (AI-verified draft)

Generate pin constraint file for target board

Run place and route

Index project

Run sim

Plugin quality auditor — scans the entire GateFlow plugin for gaps, inconsistencies, missing features, stale content, and improvement opportunities. Produces a prioritized report with actionable fixes. Example: "audit the plugin", "what's missing", "find gaps in GateFlow"

Plugin hole-plugger — takes audit findings and automatically fixes gaps, stubs, inconsistencies, and missing content across the plugin. Works as a sub-agent that receives issues and implements fixes. Example: "fix all plugin gaps", "plug the holes", "auto-fix audit findings"

KiCad schematic and PCB generation specialist. Creates AI-verified draft schematics and PCB layouts with self-improving verification loop. Example requests: "design a breakout board for iCE40", "create schematic for FPGA dev board"

SystemVerilog RTL architect - Creates synthesizable modules and hardware blocks. This agent should be used when the user wants to create new SystemVerilog modules, implement FSMs, FIFOs, arbiters, pipelines, or any RTL design from scratch. Example requests: "create a FIFO module", "write an FSM for UART", "generate a round-robin arbiter"

RTL debug specialist - Diagnoses simulation failures and unexpected behavior. This agent should be used when the user has simulation issues, X-value propagation, timing problems, or code that doesn't work as expected. Example requests: "why is my output X", "simulation is stuck", "debug this failure"

Full-stack RTL developer - Handles complex multi-file implementation tasks. This agent should be used when the user has a large feature requiring multiple files, architectural changes, or coordinated modifications across the codebase. Example requests: "implement the memory subsystem", "add DMA support", "build the interface layer"

Formal verification specialist - Generates SVA properties from natural language and configures SymbiYosys proofs. This agent should be used when the user wants to formally verify properties, prove correctness, or find counterexamples. Example requests: "prove the FIFO never overflows", "formally verify the handshake protocol", "check that the counter never exceeds MAX"

IP block scanner and auto-filler. Analyzes hardware codebases to detect missing modules, identify standard IP patterns, find CDC violations, and generate implementations. Works as a skill that other agents can invoke. Example: "scan for missing IP", "what modules need implementing", "find and fill IP gaps", "detect CDC violations"

Parallel RTL orchestrator - Decomposes designs into components and builds them in parallel. This agent is the **default build engine** after planning, even for single-module tasks (single-module = one component in Phase 1). Example requests: "build a RISC-V CPU", "create a complete SoC", "implement a multi-module subsystem"

Pin assignment specialist - Generates FPGA constraint files with correct pin mappings, I/O standards, drive strength, and slew rate for target boards. Example requests: "map SPI to PMOD JA on Arty A7", "generate constraints for iCEBreaker"

SystemVerilog planning agent - asks clarifying questions and produces a detailed RTL architecture plan before any coding. Use for requests like "plan a DMA", "design a UART", "architect a subsystem", or "how should I implement X".

Code quality engineer - Refactors, optimizes, and fixes SystemVerilog code. This agent should be used when the user wants to clean up code, fix lint warnings, improve coding style, or optimize existing RTL. Example requests: "fix these lint errors", "refactor this module", "clean up the code style"

Synthesis optimization specialist - Runs Yosys synthesis, reports area/timing, and helps with synthesis-specific issues like unsupported constructs. Example requests: "synthesize my design", "what's the area estimate", "optimize for fewer LUTs"

Verification engineer - Creates testbenches and simulation environments. This agent should be used when the user wants to write testbenches, create test stimulus, add self-checking logic, or build verification infrastructure. Example requests: "write a testbench for the ALU", "create tests for my FIFO", "add self-checking to TB"

SystemVerilog tutor - reviews solutions, gives hints, teaches concepts

RTL analyst - Explains and documents SystemVerilog code architecture. This agent should be used when the user wants to understand existing code, trace signal flows, analyze FSM behavior, or get architectural explanations. Example requests: "explain this module", "how does this FSM work", "trace the data path"

Verification methodologist - Adds assertions, coverage, and formal properties. This agent should be used when the user wants to add SVA assertions, functional coverage, cover properties, or formal verification constraints. Example requests: "add assertions for the handshake", "create coverage for FSM states", "write SVA properties"

Terminal visualization agent - Renders interactive ASCII/Unicode diagrams of RTL architecture. This agent should be used when the user wants to explore codebase visualizations interactively, navigate between hierarchy views, FSM diagrams, and module detail cards. Example requests: "visualize the codebase", "show module hierarchy", "explore the FSMs", "show me uart_tx"

VHDL code generation specialist - Creates synthesizable VHDL entities and architectures. This agent should be used when the user wants to create new VHDL modules, implement FSMs, FIFOs, or any RTL design in VHDL. Example requests: "create a VHDL counter", "write a VHDL UART", "generate VHDL entity"

VHDL testbench specialist - Creates VHDL testbenches and simulation environments. This agent should be used when the user wants VHDL testbenches, stimulus generation, or verification infrastructure in VHDL. Example requests: "write a VHDL testbench for the counter", "create VHDL test stimulus"

Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hierarchy"

Parallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates. Example: "/gf-build RISC-V CPU with ALU, regfile, decoder, control FSM"

Python-based testbench generation using Cocotb. Alternative to SystemVerilog testbenches for Python-native hardware engineers. Example: "create a cocotb test for the FIFO", "write Python testbench"

Error translation layer for hardware tool outputs. Converts cryptic Verilator, Yosys, GHDL, and simulation errors into 3-layer explanations. Used internally by gf orchestrator — not user-invocable directly.

Expand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context.

Formal verification from natural language. Generates SVA properties, configures SymbiYosys, runs proofs, and explains results. Example: "formally verify the FIFO never overflows"

FuseSoC build system integration. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source). Example: "create a FuseSoC core file", "build with Edalize"

Auto-detect IP blocks within FPGA and hardware codebases. Scans for module instantiations, identifies missing implementations, matches standard IP patterns, and dispatches agents to fill gaps. Example: "scan for missing IP blocks", "detect what needs implementing", "find unimplemented modules", "auto-fill IP blocks"

IP block library manager. Install, list, and query verified drop-in hardware components. Each block includes RTL, testbench, formal properties, and documentation. Example: "add a FIFO to my project", "/gf-ip add uart"

Contextual learning — micro-lessons embedded in workflow output. Explains hardware concepts on first encounter, tracks what has been taught, generates practice exercises on demand. Used internally by orchestrator — not typically invoked directly.

SystemVerilog learning mode - generates exercises, reviews solutions

SystemVerilog lint checker with structured output for orchestration. Runs Verilator lint, categorizes errors/warnings, explains issues, and returns a parseable result block for /gf orchestration.

KiCad schematic and PCB generation from natural language. AI-verified drafts with DRC/ERC/AI review loop. Example: "design a breakout board for iCE40 with SPI flash and 2 PMODs"

Board-aware pin mapping. Generates FPGA constraint files (.xdc/.pcf/.lpf/.cst) with correct pin assignments, I/O standards, and drive strength for target boards. Example: "map SPI to PMOD JA on Arty A7", "generate constraints for my iCEBreaker"

Hardware design planner - Creates comprehensive RTL implementation plans. This skill should be used when the user wants to plan a new design, architect a complex feature, or understand how to implement hardware before coding. Example requests: "plan a DMA controller", "design a UART", "architect the memory subsystem"

Place and route with nextpnr for open-source FPGA targets. Supports iCE40, ECP5, and Gowin devices. Example: "place and route for iCEBreaker", "run P&R targeting ice40"

Manages .gateflow/project.yaml for project-specific configuration. Auto-detects project settings or prompts user for board, HDL, and target. Used internally by other skills — not typically invoked directly.

Protocol scaffolding library. Generates correct, readable protocol interface scaffolds (AXI4-Lite, SPI, UART, I2C, AXI4-Full, AXI-Stream, Wishbone) with testbench templates and integration examples. Example: "create an I2C master interface", "scaffold AXI-Stream source"

Intent router and expand mode orchestrator for GateFlow. Classifies user intent semantically, determines confidence, triggers expand mode for ambiguous requests, and hands off to appropriate skill/agent.

SystemVerilog simulator with structured output for orchestration. Auto-detects DUT vs testbench, compiles with Verilator, runs simulation, and returns a parseable result block for /gf orchestration.

Summarize Verilator/lint output in a readable format

Synthesize SystemVerilog/Verilog with Yosys. Reports area, timing, and resource utilization. Warns about unsupported SV constructs. Example: "synthesize my design for iCE40"

Terminal visualization for GateFlow codebase maps. Renders module hierarchies, FSM state diagrams, and module detail cards as interactive ASCII/Unicode art. Example requests: "visualize the codebase", "show hierarchy", "show FSM", "show module detail"

Primary SystemVerilog orchestrator. Handles all RTL tasks end-to-end - routes to agents, runs verification, iterates until working. Examples: "create a FIFO", "test my UART", "fix lint errors", "implement and verify"

Testbench verification best practices and patterns. This skill should be used when the user needs testbench architecture guidance, verification methodology, or wants to write professional-quality testbenches. Example requests: "testbench best practices", "how to structure TB", "verification patterns"

6 hooks across 5 events