From gateflow
Orchestrates parallel SystemVerilog RTL design builds: decomposes into independent modules, spawns code-gen agents, lints, verifies components, and integrates top-level. Use /gf-build for RISC-V CPUs or similar.
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowThis skill is limited to using the following tools:
You orchestrate RTL builds by decomposing designs and spawning parallel agents.
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You orchestrate RTL builds by decomposing designs and spawning parallel agents.
User says: /gf-build <design description>
Analyze the request and identify:
## Design Decomposition: [Name]
### Shared Resources (Phase 0)
| File | Purpose |
|------|---------|
| pkg.sv | Common types, opcodes |
### Independent Components (Phase 1 - Parallel)
| Component | File | Agent | Dependencies |
|-----------|------|-------|--------------|
| ALU | alu.sv | sv-codegen | pkg |
| RegFile | regfile.sv | sv-codegen | pkg |
| ImmGen | imm_gen.sv | sv-codegen | pkg |
### Dependent Components (Phase 2 - Parallel)
| Component | File | Agent | Dependencies |
|-----------|------|-------|--------------|
| Decoder | decoder.sv | sv-codegen | pkg |
| Control | control.sv | sv-codegen | pkg, decoder |
### Integration (Phase 3)
| File | Purpose |
|------|---------|
| top.sv | Connects all components |
### Verification (Phase 4 - Parallel)
| Testbench | Tests |
|-----------|-------|
| tb_alu.sv | ALU operations |
| tb_top.sv | Integration |
I've decomposed your design into [N] components across [M] phases.
Phase 1 will spawn [X] parallel agents.
Proceed with parallel build?
If the design decomposes to a single module:
mkdir -p rtl tb
Spawn sv-codegen to create shared package (stay consistent with agent-only rule).
CRITICAL: Spawn ALL Phase 1 agents in a SINGLE message with multiple Task calls.
<Task 1>
subagent_type: gateflow:sv-codegen
prompt: |
## Component: ALU
[full spec...]
Write to: rtl/alu.sv
</Task 1>
<Task 2>
subagent_type: gateflow:sv-codegen
prompt: |
## Component: Register File
[full spec...]
Write to: rtl/regfile.sv
</Task 2>
<Task 3>
subagent_type: gateflow:sv-codegen
prompt: |
## Component: Immediate Generator
[full spec...]
Write to: rtl/imm_gen.sv
</Task 3>
Run lint on all components:
Skill: gf-lint
args: rtl/alu.sv rtl/regfile.sv rtl/imm_gen.sv
Parse results. For any failures, spawn sv-refactor agents in parallel.
Either:
Spawn testbench agents in parallel:
<Task 1> sv-testbench for ALU
<Task 2> sv-testbench for RegFile
<Task 3> sv-testbench for top
Run simulations (can be parallel):
Skill: gf-sim tb/tb_alu.sv rtl/alu.sv
Skill: gf-sim tb/tb_top.sv rtl/*.sv
## Build Complete
### Files Created
| Phase | File | Status |
|-------|------|--------|
| 0 | rtl/pkg.sv | ✓ |
| 1 | rtl/alu.sv | ✓ lint-clean |
| 1 | rtl/regfile.sv | ✓ lint-clean |
| 1 | rtl/imm_gen.sv | ✓ lint-clean |
| 3 | rtl/cpu.sv | ✓ lint-clean |
| 4 | tb/tb_cpu.sv | ✓ sim-pass |
### Parallel Efficiency
- Phase 1: 3 agents parallel (vs 3 sequential)
- Phase 4: 2 agents parallel (vs 2 sequential)
### Next Steps
- Run full simulation: `verilator --binary rtl/*.sv tb/tb_cpu.sv`
- Add assertions: `/gf add assertions to cpu.sv`
## Component: [NAME]
## Context
Part of: [parent design]
Package: [package to import]
## Specification
[Detailed functional spec]
## Interface
```systemverilog
module [name] #(
parameter int PARAM = VALUE
) (
input logic clk,
input logic rst_n,
// [grouped ports]
);
Write to: [path]
### sv-testbench Component Prompt
```markdown
## Testbench for: [DUT_NAME]
## DUT Location
rtl/[dut].sv
## Test Scenarios
1. [Test case 1]
2. [Test case 2]
3. [Edge case]
## Self-Checking
- Compare expected vs actual
- Use assertions
- Report pass/fail
## Output
Write to: tb/tb_[dut].sv
| Error | Action |
|---|---|
| Agent timeout | Retry once, then ask user |
| Lint failure | Spawn sv-refactor, re-lint |
| Sim failure | Spawn sv-debug, then sv-refactor |
| Integration mismatch | Check interfaces, fix manually |
| 2 consecutive failures | Ask user for guidance |
---GATEFLOW-RETURN---
STATUS: complete
SUMMARY: Built [design] with [N] components in [M] parallel phases
PARALLEL_SPEEDUP: [X]x (spawned N agents vs sequential)
FILES_CREATED:
- rtl/pkg.sv
- rtl/alu.sv
- rtl/regfile.sv
- rtl/cpu.sv
- tb/tb_cpu.sv
VERIFICATION:
- Lint: PASS (0 errors, 0 warnings)
- Sim: PASS (all tests)
---END-GATEFLOW-RETURN---