From gateflow
Manages .gateflow/project.yaml for HDL projects: auto-detects HDL type from extensions (SystemVerilog/Verilog/VHDL), sources, top module; sets board, device, clock. Used internally by other Gateflow skills.
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowThis skill uses the workspace's default tool permissions.
`.gateflow/project.yaml` in the project root.
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.gateflow/project.yaml in the project root.
name: my-project
top_module: top
hdl: systemverilog # systemverilog | verilog | vhdl
target:
board: null # arty-a7-35t, icebreaker, etc.
device: null # xc7a35ticsg324-1L, ice40hx8k, etc.
clock_freq: null # 100MHz, 12MHz, etc.
sources: [] # auto-populated by gf-scan
constraints: null # path to constraint file
ip_blocks: [] # installed IP block names
When this skill is invoked, it:
.gateflow/project.yaml exists.sv = systemverilog, .v = verilog, .vhd = vhdl)**/*.sv, **/*.v, **/*.vhdAny skill that needs project context should:
cat .gateflow/project.yaml 2>/dev/null
If the file doesn't exist, invoke this skill to create it.
When a user mentions a board name in natural language (e.g., "I'm using an Arty A7"),
persist it to .gateflow/project.yaml under target.board. Do not ask again unless
the user switches boards or starts a new project.
Board memory is per-project, not global. Different projects target different boards.