rtl-agent-team

Block-level architecture designer for RTL projects — block diagrams, interfaces, data flow (Opus)

Full RTL design pipeline orchestrator. Manages 6-phase flow with dual-layer phase gates, parallel agent execution, feedback loops, and resumability. Spawns specialist agents for each phase and enforces quality gates between phases.

SystemC Bus Functional Model developer for TLM-2.0 AT non-blocking models with ARM AMBA protocol support (AXI/AHB/APB/ACE), payload pooling, and DPI-C co-simulation

CDC static analysis specialist. Detects clock domain crossings, verifies synchronizer presence, and analyzes RTL AST with slang for metastability risks.

CDC design strategy reviewer. Evaluates synchronization architecture quality, FIFO depth calculations, metastability budgets, and reset synchronization. Produces review reports in reviews/.

Clock and reset architecture specialist. Reviews clock tree design, clock distribution strategy, clock gating structure, PLL/MMCM configuration, clock mux safety, skew budgets, reset tree topology, reset synchronization, and reset sequencing. Produces review reports in reviews/.

cocotb testbench quality reviewer. Reviews Python test code quality, stimulus generation, assertion patterns, async/await correctness, BFM integration, and cocotb-specific pitfalls. Produces review reports in reviews/.

Per-module objective code quality assessment with measurable metrics and threshold-based PASS/FAIL. Produces reviews/phase-6-review/code-review.md. Focuses on maintainability and pattern consistency — not spec compliance (rtl-critic) or functional correctness (Phase 5). (Opus)

Cross-review orchestrator using Codex CLI as 2nd reviewer. Runs structured finding exchange with consensus loop (max 5 rounds), then user escalation.

Independent compliance verification agent — compares downstream artifacts against upstream iron requirements

SDC/XDC constraint auto-generation from RTL analysis. Defines clocks, false paths, multicycle paths, and I/O timing constraints.

Code and functional coverage analysis specialist. Identifies test gaps, ranks uncovered bins by risk, and drives coverage convergence strategy.

Thin wrapper around skills/rtl-ppa-optimize-dc/scripts/parse_dc_reports.py. Invokes the parser on syn/rpt/ and returns syn/ppa-report.json location plus a terse JSON summary. No RTL modification.

Comprehensive design documentation writer. Produces reviews/phase-6-review/design-note.md with full module descriptions, Mermaid diagrams, algorithm explanations, and system-level integration overview. (Opus)

Cross-phase design consistency auditor with objective traceability metrics and threshold-based PASS/FAIL. Produces reviews/phase-6-review/design-review.md. Verifies Spec→Arch→μArch→RTL hierarchical coherence. (Opus)

Design for Testability (DFT) specialist. Designs scan chain architecture, BIST logic, JTAG integration, test point insertion, and production test strategies. Reviews DFT readiness of RTL.

Generic domain expert runner — loads expert definition from prompt for dynamically discovered local experts in domain-packages

Iterative Design Space Exploration orchestrator. Manages Phase 1→3 with deep algorithm study, architecture candidates, μArch + BFM, self-critique loop, and user satisfaction check. Produces pre-implementation package (not RTL).

Runs Verilator, Yosys, SymbiYosys, cocotb via Bash CLI. Parses logs, classifies errors, suggests fixes.

Equivalence checking specialist. Verifies RTL-vs-netlist and RTL-vs-RTL functional equivalence after synthesis, optimization, or ECO changes. Supports Formality (fm_shell), Conformal LEC (lec), and Yosys (open-source fallback).

Formal verification quality reviewer. Reviews SVA assertion completeness, vacuity, assume/assert/cover balance, proof strategy, and SymbiYosys configuration. Produces review reports in reviews/.

cocotb-based functional verification expert. Compares RTL simulation outputs against C/Python reference models for bitexact agreement. Produces regression results, requirement traceability matrices, and coverage reports.

Identifies improvement opportunities from Phase 6 reviews and produces prioritized recommendations with Impact×Effort matrix. Produces reviews/phase-6-review/improvements.md. (Opus)

Integration and top-level verification specialist. Verifies sub-module connectivity, port width matching, signal naming consistency, and hierarchical integration correctness. Produces integration reports in reviews/.

IP-XACT IEEE 1685 XML generator. Produces component descriptions from RTL port lists and register maps for EDA tool integration.

Annotate key moments with RAT (Reasoning Audit Tag) markers for traceable decision records.

Follow the structured output annotation protocol defined in `agents/lib/audit-output-protocol.md`.

Follow the structured output annotation protocol defined in `agents/lib/audit-output-protocol.md`.

Follow the structured output annotation protocol defined in `agents/lib/audit-output-protocol.md`.

Follow the structured output annotation protocol defined in `agents/lib/audit-output-protocol.md`.

Follow the structured output annotation protocol defined in `agents/lib/audit-output-protocol.md`.

Cross-file lint pattern analyzer. Runs Verible + slang dual lint, identifies root causes across multiple files, and provides actionable fix guidance. (Opus)

Phase 1 research pipeline orchestrator. Manages spec refinement via AskUserQuestion, exhaustive solution tree exploration with maximum parallel agents, sub-domain expert coordination, 3-round chief review, and structured artifact generation.

Phase 1 research team coordination teammate. Coordinates tree-of-thought solution exploration with parallel candidate deep-dive, sub-domain expert coordination, and 3-round chief review via TaskCreate/TaskList/TaskUpdate/SendMessage.

Phase 2 architecture pipeline orchestrator. Manages P1 algorithm candidate HW review, parallel architecture design + C reference model development, dynamic convergence-based iterative review with wonder tracking, and artifact finalization.

Phase 2 architecture team coordination teammate. Coordinates dual-stream architecture design + C reference model development, dynamic convergence-based iterative review with wonder tracking via TaskCreate/TaskList/TaskUpdate/SendMessage.

Phase 3 μArch design pipeline orchestrator. Manages parallel uarch design + BFM development, BFM validation gate, dynamic convergence-based review with wonder tracking, upstream feedback report, domain consultation for design patterns, and artifact finalization with clock domain map, protocol assignments, and pipeline diagrams.

Phase 3 uArch design team coordination teammate. Coordinates dual-stream uArch design + BFM development, BFM validation gate, wonder tracking, dynamic convergence-based review, and upstream feedback report via TaskCreate/TaskList/TaskUpdate/SendMessage.

Phase 4 block-parallel coordination teammate. Manages 6 worktree-based block workers, upstream-first merge sequence, contract test orchestration, and design freeze verification via TaskCreate/TaskList/TaskUpdate/SendMessage.

Per-block worktree execution worker for Phase 4 block-parallel development. Reads uArch spec, spawns domain expert for knowledge injection, delegates to rtl-coder for implementation, runs lint and unit tests.

Phase 4 RTL implementation orchestrator. Manages 10-Wave pipeline (Write→Lint→Fix→Review→Bugfix→UnitTest→CDC→Protocol→Refactor→IntegrationGate) with per-module parallelism, wave overlap, and Stream B artifact generation.

Phase 4 RTL implementation team coordination teammate. Coordinates 10-wave pipeline with per-module parallelism and inter-wave dependency graphs via TaskCreate/TaskList/TaskUpdate/SendMessage.

Phase 4 rapid RTL and sanity integration orchestrator. Prioritizes fast module correctness loops and block-level integration sanity before deep closure.

RTL bug fix orchestrator. Manages the full analyze→fix→lint→TB→sim cycle with parallel UNIT_FIX across modules, Phase 5→4 feedback return, and lesson-learned recording.

RTL refactoring orchestrator. Manages the analyze→refactor→lint→equivalence cycle for structural RTL improvements without behavioral change.

Tier 2 unit test orchestrator. Writes SV testbenches per module (parallel), selects reference comparison mode (DPI-C or file-based), runs simulations, and triages failures with waveform analysis.

Phase 5 verification orchestrator. Manages three-stage (module→top→final) parallel verification pipeline with 9 verification categories, module graduation gates, feedback loops, and compliance review.

Phase 5 verification team coordination teammate. Coordinates parallel verification across 9 categories with dependency graphs and module graduation gates via TaskCreate/TaskList/TaskUpdate/SendMessage.

Phase 5A functional closure orchestrator. Executes deep hierarchy-level functional verification, coverage closure, and requirement traceability gates.

Phase 5B silicon validation orchestrator. Runs block/top synthesis and signoff-oriented checks after functional closure pass.

CDC verification orchestrator. Manages clock domain identification, cross-domain path analysis, synchronizer verification, SDC constraint generation, and optional commercial CDC tool integration.

Coverage analysis orchestrator. Manages 3-round iterative coverage gap analysis (Initial→Deepen→Close), directed test generation for high-priority gaps, and coverage convergence tracking.

Tier 3 functional verification orchestrator. Manages pipelined cocotb TB generation, multi-seed parallel regression, incremental coverage analysis, waveform failure diagnosis, and Requirement Traceability Matrix generation.

Tier 4 integration test orchestrator. Manages static connectivity verification, dynamic data flow and handshake tests, end-to-end reference comparison, and failure triage across module boundaries.

Performance verification orchestrator. Manages RTL performance simulation, BFM baseline comparison, throughput/latency/stall measurement, and deviation flagging (>10% threshold).

Protocol compliance verification orchestrator. Manages bus interface identification, SVA protocol assertion generation, assertion binding, simulation-based checking, and violation reporting for AXI/AHB/APB.

SVA/formal verification orchestrator. Manages 3-round iterative property refinement (Draft→Strengthen→Harden), sv2v conversion, SymbiYosys BMC/induction dispatch, and counterexample diagnosis.

UVM verification orchestrator. Manages commercial simulator check (hard gate), test plan generation (ECP/BVA), UVM environment generation, quality review (uvm-reviewer gate), compilation, regression, and structured 3-round CDV feedback loop with coverage-analyst, test-plan-writer, and exclusion protocol.

Phase 6 design review orchestrator. Manages 2-wave parallel execution (code-quality + design-quality → CC1 → design-note + improvements → CC2) with consistency checks and completion quality gate.

Phase 7 free exploration orchestrator. Manages guard rail enforcement, exploration agent dispatch, ADR creation, and result documentation. Exempt from pipeline rules (Rule 9).

Performance verification specialist measuring RTL latency and throughput against BFM cycle-accurate targets

Power analysis specialist. Reviews clock gating effectiveness, switching activity, power domain strategy, leakage/dynamic power estimates, and power budget compliance. Produces review reports in reviews/.

Coordinator for one PPA optimization iteration. Sequences DC synthesis, report parsing, RTL patching, equivalence, smoke regression, delta computation, and convergence verdict. Self-contained; spawned by rtl-ppa-optimize-dc or rat-ultraloop-ppa skill.

DC-based PPA optimization RTL patcher. Reads ppa-report.json + RTL + requirements.json, emits RTL unified diff + rationale + DC Tcl snippet. Timing-first heuristic. Never modifies files outside allowed_edit_scope.

AXI/AHB/APB protocol verification specialist. Writes protocol-specific SVA assertions and validates handshake timing compliance.

Bus protocol interface design reviewer. Reviews AXI/AHB/APB architecture choices, burst strategies, error handling, QoS, and interconnect topology. Produces review reports in reviews/.

C functional reference model developer — no clock/reset, external memory abstraction, DPI-C compatible

Reference model quality reviewer. Primarily reviews C reference models (project default); also supports C++/Python. Checks numerical accuracy, algorithm fidelity to spec, and test oracle reliability. Produces review reports in reviews/.

Regression analysis specialist. Tracks multi-seed pass/fail trends, detects flaky tests, analyzes coverage convergence, and identifies seed-bug correlations. Produces regression reports in reviews/.

Requirement traceability specialist. Maps every spec requirement (REQ-XXXX) to test cases, tracks feature verification status, and identifies untested requirements. Produces traceability matrix reports in reviews/.

LLM review and controlled refactor orchestrator. Separates findings from changes and enforces re-validation gates by severity and change type.

Architecture review oracle for RTL designs. Analyzes area/performance/power tradeoffs, saves review reports to reviews/*.md with Mermaid diagrams. Every finding cites file:line. (Opus)

SystemVerilog RTL coder (lowRISC style + project overrides). Writes synthesizable, lint-clean RTL following project conventions (snake_case, i_/o_ prefixes, clk/{domain}_clk, rst_n/{domain}_rst_n, typedef enum/struct packed, u_ instances, UPPER_CASE params, always_ff/always_comb). One module per file. Runs lint after every write.

Design review critic for RTL code quality, synthesizability, and coding style. Saves review reports to reviews/*.md. (Opus). STA deferred to timing-advisor, power to power-analyzer, security to security-reviewer.

RTL codebase explorer. Maps module hierarchy, traces signals across boundaries, and builds dependency maps using Glob, Grep, and LSP tools.

RTL project planner. Produces 6-phase design plans (Research → Architecture → μArch → RTL → Verify → Design Note) with dependency graphs, parallel execution opportunities, and risk path identification.

Hardware security reviewer. Reviews RTL for side-channel vulnerabilities, fault injection resilience, secure reset/boot, secret handling, and OWASP hardware security risks. Produces security review reports in reviews/.

RTL specification analysis expert that transforms raw spec docs into structured requirements. Saves self-validation reports to reviews/*.md with Mermaid diagrams. (Opus)

Phase 1→3 pipeline orchestrator. Manages Research → Architecture → μArch flow with dynamic convergence-based reviews per phase, dual-layer phase gates, phase coherence feedback loops, ADR recording, parallel sub-pipeline execution, and resumability. Stops before Phase 4.

Phase 1-3 pipeline orchestrator (sequential mode only). Manages Research, Architecture, uArch sequentially with inter-phase quality gates, ADR recording, and resumability. In team mode, the skill handles phase sequencing directly. Stops before Phase 4.

SVA assertion extraction from spec. Writes .sva bind files. Runs SymbiYosys BMC + induction to prove or find counterexamples.

Yosys synthesis report parser. Extracts area, timing, and power metrics. Produces summary tables and identifies unmapped cells.

Synthesis results design reviewer. Reviews area/timing/resource utilization, evaluates critical paths, assesses optimization opportunities, and judges architectural trade-offs. Produces review reports in reviews/.

Test plan generation specialist — derives test scenarios from uarch spec using ECP/BVA/STT/DT methodology

SV testbench and cocotb testbench developer. Designs coverage models, stimulus generators, and covergroups. Ensures functional coverage closure.

Static Timing Analysis (STA) advisor. Critical path identification, pipeline depth analysis, logic level estimation, fanout analysis, false/multi-cycle path detection, SDC constraint review. Never writes code. (Opus, READ-ONLY). CDC analysis is handled by cdc-checker and cdc-reviewer.

Microarchitecture designer for FSMs, pipelines, datapaths, and register maps (Opus)

Phase 4→5 pipeline orchestrator. Manages RTL implementation (dual-stream) and verification (5 sub-phases) with prerequisite checks, dual-layer phase gates, Phase 5→4 feedback loops, and resumability. Stops before Phase 6.

Autonomous review agent for rat-ultraloop. Reviews RTL implementation quality, contract test coverage, and design freeze integrity. Strictly READ-ONLY.

UVM testbench quality reviewer. Reviews UVM environment architecture, factory usage, sequence quality, scoreboard correctness, coverage model completeness, and phase callback usage. Produces review reports in reviews/.

Codec HW architecture expert. Proven video codec architectures from IEEE literature. SRAM organization, fixed-point arithmetic, HW-friendly algorithm modifications. Participates in Research ★☆☆, Architecture ★★★, μArch ★★★, RTL ★★☆, Verify ★☆☆.

Video codec chief standard expert. Reviews and coordinates outputs from 6 sub-domain experts (vcodec-syntax-entropy, vcodec-intra-pred, vcodec-me, vcodec-mc, vcodec-transform-quant, vcodec-filter-recon). Identifies cross-block dependencies, resolves conflicts, and iterates until requirements are Architecture-ready.

Video codec in-loop filter and reconstruction path expert (H.264/H.265). Interprets deblocking filter, SAO, boundary strength calculation, filter decision logic, and pixel reconstruction pipeline from normative standard text.

Video codec intra prediction expert (H.264/H.265). Interprets intra prediction modes, reference sample construction, mode-dependent filtering, and boundary conditions from normative standard text.

Video codec motion compensation expert (H.264/H.265). Interprets sub-pixel interpolation filters, bi-prediction weighting, weighted prediction, and reference block fetching from normative standard text.

Video codec motion estimation expert (H.264/H.265). Interprets ME search algorithms (IME/FME), MV prediction (AMVP/merge), reference frame management, and search range constraints.

Video codec syntax and entropy coding expert (H.264/H.265). Interprets NAL unit structure, slice headers, CABAC/CAVLC context models, binarization tables, and DPB management from normative standard text.

Video codec transform and quantization expert (H.264/H.265). Interprets integer DCT/DST, scaling matrices, QP-dependent quantization, RDOQ, inverse transform, and fixed-point arithmetic constraints from normative standard text.

Video codec hardware performance analysis expert. Advises on codec throughput (MB/s, CTU/s), memory bandwidth budgets, cycles-per-block analysis, DPB sizing, line-buffer sizing, pipeline parallelism, and clock frequency targeting for H.264/H.265 encoder and decoder hardware.

Color format conversion expert for video processing hardware. Advises on RGB/YUV/Bayer conversions, BT.601/BT.709/BT.2020 color spaces, chroma subsampling (4:2:0/4:2:2/4:4:4), and bit-depth conversion (8-bit to 10/12-bit) with fixed-point RTL implementation guidance.

Video/image denoising expert for hardware implementation. Advises on spatial noise reduction (bilateral, NLM), temporal noise reduction (3DNR, motion-adaptive), noise modeling, filter kernel design, and fixed-point implementation for real-time video denoising pipelines.

Image/video signal processing expert for hardware design. Advises on HDR tone mapping (PQ/HLG), gamma correction (OETF/EOTF), image scaling/resampling (bilinear, bicubic, Lanczos), edge enhancement/sharpening, and ISP pipeline architecture for real-time video hardware.

VCD/FST deep analysis specialist. Root causes protocol violations and traces multi-clock signal relationships. Never modifies RTL or test files.

Tier 3 module-level regression: cocotb multi-seed regression comparing RTL against reference models. Produces Requirement Traceability Matrix.

Policy rules, coding conventions, test ordering, result schema, escalation rules, and checklists for Tier 4 integration testing. Pure reference — no orchestration.

Tier 4 integration testing: full system-level verification of cross-module data flow, reset propagation, clock connectivity, and end-to-end scenarios.

Policy rules, performance monitor naming conventions, BFM comparison thresholds (10% deviation), metric definitions, and verification checklists. Pure reference — no orchestration.

This skill should be used when measuring RTL throughput and latency against BFM baselines. Flags deviations exceeding 10%.

Policy rules, AXI/AHB/APB signal naming conventions, protocol assertion patterns, key protocol rules, and verification checklists. Pure reference — no orchestration.

This skill should be used when verifying bus protocol compliance (AXI/AHB/APB) using SVA handshake and ordering rules.

This skill should be used when proving or disproving formal properties on RTL using SymbiYosys BMC and induction. Triggers on 'formal verification', 'prove property', 'SVA'.

Policy rules, SVA coding conventions, SymbiYosys engine guide, 3-round iterative refinement protocol, and formal verification checklists. Pure reference — no orchestration.

Policy rules, UVM naming conventions (m_ prefix, u_dut instance), commercial simulator requirements, coverage collection rules, and checklists. Pure reference — no orchestration.

This skill should be used when running UVM-based verification requiring commercial simulators (VCS/Questa/Xcelium).

Policy rules, design note requirements, consistency check protocol, PDF generation pipeline, escalation rules, and checklists for Phase 6 design review. Pure reference — no orchestration.

Phase 6: Design Review & Documentation with 2-round consistency checks, detailed design notes with decision rationale, and PDF generation support.

Policy rules, guard rails, scope definitions, ADR workflow, and output format for Phase 7 free exploration mode. Pure reference — no orchestration.

Phase 7: Free exploration mode for algorithm alternatives, optimization experiments, and technology evaluation. Exempt from pipeline rules (Rule 9).

One-shot Design Compiler–based PPA optimization iteration. Runs DC synthesis, parses reports into JSON, generates RTL patch, validates scope, verifies equivalence + smoke, computes delta, and emits convergence verdict. Requires Phase 5 PASS and dc_shell/genus in PATH.

LLM-based code review and controlled refactoring workflow. Separates findings, safe refactors, and mandatory re-validation gates.

Policy for P5B silicon validation. Defines block/top synthesis, constraints quality, timing-oriented checks, and signoff readiness criteria.

This skill should be used when running Yosys synthesis for area/timing estimation, synthesizability checking, or generating SDC timing constraints. Detects inferred latches, unmapped cells, and produces Design Compiler/Genus-ready SDC.

Passive simulation tool profiles for replayable execution (verilator, iverilog, vcs, xrun, questa).

Passive synthesis tool profiles (yosys, dc_shell, genus) for replayable runs and comparable summary outputs.

SystemC/TLM-2.0 coding convention and design guideline skill. Enforces coding standards for BFM development (Phase 3) and Reference Model development (Phase 2). Covers TLM-2.0 AT/LT patterns, AMBA-PV extensions, naming conventions, and testbench integration.

SVA (SystemVerilog Assertion) coding convention and formal verification guideline skill. Covers assertion styles, property/sequence patterns, bind files, coverage properties, and SymbiYosys integration. Applied when writing .sva files or SVA blocks in .sv files.

SystemVerilog coding convention and design guideline skill. Enforces lowRISC style + project overrides for all .sv/.v file generation. Covers naming, module structure, power optimization, FPGA considerations, and pipelining for timing closure.

Systematic test case design methodology — equivalence partitioning, boundary value analysis, state transition, decision table testing. Pure reference — no orchestration.

UVM (Universal Verification Methodology) coding convention and methodology guideline skill. Covers class hierarchy, factory patterns, sequence/sequencer, TLM ports, coverage integration, and naming conventions for UVM testbenches.

Passive policy defining minimum re-validation matrix by change type after review/refactor work.

This skill should be used when conducting architecture review with area/performance/power tradeoff analysis. Saves review reports to reviews/ directory.

This skill should be used when developing SystemC TLM Bus Functional Models with AT non-blocking transport and AMBA protocol support from architecture block specifications.

Passive CDC tool profiles (structural, svlens, spyglass, vc_cdc, questa_cdc) and classification conventions. Includes svlens conn/metrics modes.

Passive policy for LLM code review findings, severity taxonomy, and evidence format.

Decoder conformance evaluation against JVET/JCTVC/3rd-party conformance bitstreams. Builds ref C model decoder, runs parallel decoding, and verifies bitexact output match against golden references. Supports profile/level filtering, MD5/bitexact/PSNR comparison, optional SSIM/VMAF, and AWS Batch opt-in.

Rate-Distortion evaluation automation for codec algorithm comparison. Builds ref C model encoder, runs parallel encoding simulations across multiple sequences and QP points, computes BD-PSNR/BD-rate (VCEG-M33 methodology), and generates comparison reports. Supports N-candidate comparison, configurable encoder CLI, SSIM/VMAF opt-in metrics.

Cross-review with Codex CLI as 2nd reviewer. Structured finding exchange, consensus loop (max 5 rounds), user escalation. Manual or auto-invoked at phase boundaries.

Cross-phase spec consistency validation. Verifies P3 uarch → P4 RTL → P5 verification artifact contracts: port widths, memory classification, pipeline depth, bus parameterization, REQ traceability.

This skill should be used when consulting domain experts for codec standards, video processing, or fixed-point math questions.

Passive lint tool profiles (verilator, verible, slang, spyglass) with unified report expectations.

Quality criteria, review protocols, naming conventions, artifact format specifications, and checklists for the Phase 1 research pipeline. Pure reference — no orchestration.

Phase 1 spec research. Refines spec precisely, collects missing information via AskUserQuestion and domain-consult, surveys candidate algorithms/tools with trade-offs, and proposes options matching user requirements.

Architecture review criteria, HW candidate evaluation methodology, naming conventions, and checklists for the Phase 2 architecture design pipeline. Pure reference — no orchestration.

Phase 2 architecture design. Reviews P1 algorithm candidates for HW implementation feasibility, designs block-level data paths, builds reference C model, and iterates with 3-round review.

Policy rules, weights defaults, timing-first heuristic, convergence criteria, DC Tcl fragments, and rollback protocol for the DC-based PPA optimization pipeline. Pure reference — no orchestration.

Policy rules, phase gate definitions, quality criteria, feedback loop classification, and checklists for the RTL autopilot 6-phase pipeline. Pure reference — no orchestration.

This skill should be used when starting a full RTL design pipeline from spec to verification. Orchestrates 6-phase flow (Research → Architecture → μArch → RTL → Verify → Design Note) with dual-layer phase gates and hierarchical spec compliance.

Policy rules, DSE methodology, comparison matrix formats, C model transformation rules, self-critique protocol, trial comparison, and gate criteria for the iterative Design Space Exploration pipeline (Phase 1→3). Pure reference — no orchestration.

Iterative Design Space Exploration covering Phase 1→3: spec analysis, algorithm study, architecture exploration, μArch design, and C/SystemC BFM creation. Self-critique loop with user-controlled trial iteration and worktree-based comparison.

This skill should be used when initializing a new RTL project with directory structure, rules, guides, and template files. Triggers on 'init project', 'initialize project', 'new project', 'project init'.

Policy rules, phase gate definitions, cascading quality protocol, handoff checklist, and ADR requirements for the Phase 1→3 pipeline. Pure reference — no orchestration.

Phase 1-3 pipeline using native teams for parallel execution within each phase. Sequences P1 research team, P2 architecture team, P3 uArch team with inter-phase quality gates.

This skill should be used when completing design documents from spec through microarchitecture (Phase 1→3). Produces research artifacts, block architecture, reference model, microarchitecture specs, and BFM with full quality gates and 3-round iterative reviews — stopping before RTL implementation for human review.

Policy rules, prerequisite definitions, phase gate criteria, feedback loop classification, and checklists for the Phase 4→5 pipeline. Pure reference — no orchestration.

This skill should be used when implementing RTL and running verification from existing microarchitecture documents (Phase 4→5). Requires completed Phase 1-3 artifacts as prerequisites. Produces RTL code, unit tests, and full verification with Phase 5→4 feedback loops — stopping before Design Note phase.

Plugin diagnostics: version, EDA tool status, state files, hook health. Use when troubleshooting setup or verifying environment.

This skill should be used when verifying EDA toolchain installation, installing missing tools, or building the Docker EDA image. Triggers on 'setup tools', 'install tools', 'EDA setup', 'docker image'.

Interactive tutorial for RTL Agent Team. Explains key commands, 6-Phase pipeline, domain expert extension, and team mode. Auto-detects user language; append a language name to override (e.g., /rtl-agent-team:rat-tutorial Korean).

Auto-loop wrapper for DC-based PPA optimization. Repeats rtl-ppa-optimize-dc until convergence, early-plateau escalation, or max_cycles. 30-min auto-continue support. Emits final report + marks rtl-verify-done on normal convergence.

Autonomous implement-review-improve loop with 30-min auto-continue and design freeze enforcement. Wraps target skills for unattended execution.

This skill should be used when building C functional reference models (no clock/reset) with external memory access abstraction and bitexact verification. DPI-C integration priority.

Passive policy classifying RTL refactoring changes into SAFE/RESTRICTED/PROHIBITED tiers with approval requirements. Used by review-refactor workflow.

Policy skill defining contract test structure, merge-time verification procedures, and stub generation rules for block-parallel development.

Policy skill defining interface design rules, timing contract format, and Phase 2 interface freeze criteria for block-parallel RTL development.

This skill should be used when creating minimal reproduction testbenches for RTL bugs. Isolates root cause with waveform analysis.

This skill should be used when running standards conformance tests (H.264/H.265) requiring bitexact comparison against JM/HM reference decoders.

This skill should be used when generating RTL documentation from source and synthesis reports. Produces port tables and design summaries.

This skill should be used when generating IP instantiation wrappers from IP-XACT descriptors or datasheets with convention-compliant port mapping.

This skill should be used when generating IEEE 1685 IP-XACT XML descriptors from RTL port and parameter definitions.

This skill should be used when checking RTL files for lint violations using Verilator, Verible, and slang. Quick utility for pre-commit or phase gate verification.

This skill should be used when performing 3-way consistency checks between C reference model, BFM, and RTL simulation outputs.

Internal RTL routing reference. Defines the single source of truth for Action Skill routing, Action Skill→Orchestrator→Policy mapping, and SessionStart hook export content.

Phase 1 research using Claude Code native teams for parallel tree-of-thought exploration. Manages solution tree construction, parallel candidate deep-dive, sub-domain expert coordination, and 3-round chief review.

Phase 2 architecture design using Claude Code native teams for parallel dual-stream architecture + RefC development. Manages HW candidate evaluation, parallel design streams, and 3-round iterative review with tree exploration.

Phase 3 uArch design. Concretizes P2 modules into sub-blocks with clock domains, protocol assignment, register/SRAM/FSM allocation. Validates via TLM-based BFM with per-block I/O logging.

μArch design criteria, clock domain rules, protocol assignment rules, BFM validation requirements, signal naming conventions, and checklists for the Phase 3 μArch design pipeline. Pure reference — no orchestration.

Phase 3 uArch design using Claude Code native teams for parallel dual-stream uArch + BFM development. Manages per-block uarch design, BFM validation gate, and 5-reviewer 3-round iterative review.

Phase 4 block-parallel RTL implementation using 6 worktrees with Team coordination and upstream-first merge. Requires Phase 2 interfaces and Phase 3 uArch.

Policy rules, 10-Wave pipeline definitions, coding conventions, wave overlap strategy, escalation conditions, and checklists for the Phase 4 RTL implementation pipeline. Pure reference — no orchestration.

Phase 4 RTL implementation using Claude Code native teams for parallel worker execution. Manages 10-wave pipeline with per-module parallelism and inter-wave dependency graphs.

Implement SystemVerilog RTL modules from uarch specs in Phase 4. Produces lint-clean, code-reviewed, unit-tested, CDC/protocol-checked rtl/*/*.sv through a 10-Wave pipeline.

Policy for P4 rapid RTL implementation and block sanity integration. Defines quick-loop gates, failure handling, and minimum quality bars.

Phase 4 rapid RTL implementation and sanity integration. Focuses on module design correctness, fast feedback loops, and block-level integration sanity before deep verification.

Policy rules, mandatory sequence, parallel UNIT_FIX decision tree, escalation rules, and checklists for the RTL bug fix workflow. Pure reference — no orchestration.

RTL bug fix workflow enforcing the full cycle: analyze → fix → lint → TB create/update → functional verification. Prevents RTL changes from being considered complete with lint-only validation.

Policy rules, refactoring decision criteria, naming convention audit rules, equivalence proof requirements, escalation rules, and checklists for RTL refactoring. Pure reference — no orchestration.

This skill should be used when restructuring RTL code without behavioral change. Applies naming conventions and verifies equivalence.

Policy rules, coding conventions, reference comparison modes, result schema, escalation rules, and checklists for Tier 2 unit testing. Pure reference — no orchestration.

Tier 2 unit testing: verify each RTL module against its uarch specification and C reference model. Goes beyond Tier 1 smoke to exercise FSM transitions, pipeline behavior, and data transformations.

Verification criteria, module graduation gates, coverage targets, synthesis estimation policy, and checklists for the Phase 5 three-stage verification pipeline. Pure reference — no orchestration.

Phase 5 verification using Claude Code native teams for parallel worker execution. Manages 9 verification categories with dependency-aware task graphs and module graduation gates.

Phase 5 verification orchestrator: three-stage (module→top→final) parallel verification pipeline covering lint, SVA/formal, CDC, protocol, functional regression, coverage, performance, synthesizability estimation, and code review.

Policy for P5A functional closure. Defines hierarchy-level verification depth, coverage goals, and requirement traceability gates.

Phase 5A functional verification closure across module, block, and top pre-integration checkpoints. Functional correctness is the absolute priority gate.

Phase 5B silicon validation for block/top signoff readiness. Runs synthesis, constraints, timing-oriented checks, and top integration precision checks after functional closure.

Policy rules, clock/reset naming conventions, synchronizer type selection guide, CDC violation categories, SDC constraint patterns, and checklists. Pure reference — no orchestration.

This skill should be used when analyzing clock domain crossings for synchronizer coverage and metastability risks.

This skill should be used when analyzing functional coverage reports to identify gaps and prioritize additional test generation.

Policy rules, coverage targets (90% line, 80% toggle, 70% FSM), gap prioritization heuristics, 3-round iterative refinement protocol, and checklists. Pure reference — no orchestration.

Policy rules, multi-seed strategy, coverage targets, signal naming conventions, traceability format, and checklists for Tier 3 module-level cocotb regression. Pure reference — no orchestration.

15 hooks across 6 events

slang-server