By babyworm
99-agent RTL design pipeline with 97 skills for 6-Phase hardware design automation (Research → Architecture → μArch → RTL → Verify → Design Note)
Block-level architecture designer for RTL projects — block diagrams, interfaces, data flow (Opus)
Full RTL design pipeline orchestrator. Manages 6-phase flow with dual-layer phase gates, parallel agent execution, feedback loops, and resumability. Spawns specialist agents for each phase and enforces quality gates between phases.
SystemC Bus Functional Model developer for TLM-2.0 AT non-blocking models with ARM AMBA protocol support (AXI/AHB/APB/ACE), payload pooling, and DPI-C co-simulation
CDC static analysis specialist. Detects clock domain crossings, verifies synchronizer presence, and analyzes RTL AST with slang for metastability risks.
CDC design strategy reviewer. Evaluates synchronization architecture quality, FIFO depth calculations, metastability budgets, and reset synchronization. Produces review reports in reviews/.
Phase 4-to-5 pipeline: implement RTL then verify from existing P1-3 docs, with P5-to-P4 feedback; stops before Phase 6. Trigger: 'implement and verify'.
Plugin diagnostics: version, EDA tool status, state files, hook health. Triggers: 'rat debug', 'plugin status', troubleshooting plugin behavior.
One-time EDA toolchain setup wizard: verify or install tools, build Docker EDA image. Triggers: 'setup tools', 'install tools', 'EDA setup'.
Interactive plugin tutorial: key commands, 6-phase pipeline, team mode. Auto-detects language; append a language name to override. Trigger: 'tutorial'.
Auto-loop wrapper repeating rtl-ppa-optimize-dc until PPA convergence or plateau. Triggers: 'ultraloop PPA', 'PPA auto-loop', 'optimize PPA until converge'.
Executes bash commands
Hook triggers when Bash tool is used
Modifies files
Hook triggers on file write and edit operations
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Sign in to claimnpx claudepluginhub babyworm/rtl-agent-team --plugin rtl-agent-teamBased on adoption, maintenance, documentation, and repository signals. Not a security audit or endorsement.
Uses power tools
Uses Bash, Write, or Edit tools
Uses power tools
Uses Bash, Write, or Edit tools
한국어 문서: README_kr.md
A Claude Code plugin for automated RTL design and verification. 99 specialized AI agents + 97 skills automate the 6-Phase pipeline: Research → Architecture → μArch → RTL → Verify → Design Note.
A Claude Code plugin for automated RTL design and verification.
Automates the 6-Phase design pipeline (Research → Architecture → μArch → RTL → Verify → Design Note) with 99 specialized AI agents + 97 skills + 27 reference documents.

This repository serves as the RTL Agent Marketplace, providing hardware design plugins.
| Plugin | Description | Version |
|---|---|---|
| rtl-agent-team | 99-agent RTL design pipeline (Research → Architecture → μArch → RTL → Verify → Design Note) | 0.14.1 |
| systemverilog-lsp | SystemVerilog/Verilog LSP (slang-server based — diagnostics, hover, go-to-definition, etc.) | 1.1.4 |
Additional plugins (domain knowledge packages, MCP servers, specialized skills, etc.) will be added to the Marketplace over time.
The workflow has three distinct stages, each with a different scope and frequency:
| Stage | Scope | Frequency | Commands |
|---|---|---|---|
| A. Machine Setup | Per machine (global) | Once per machine | /plugin install + /rtl-agent-team:rat-setup |
| B. Project Init | Per project directory | Once per project | /rtl-agent-team:rat-init-project |
| C. Design Work | Inside project | Recurring | /rtl-agent-team:rat-auto-design, phase/sub-skills |
Run each stage from its appropriate working directory: Stage A runs anywhere; Stages B and C should run from inside the target project directory (artifacts like docs/phase-*/, rtl/, .rat/state/ are written relative to CWD).
Installs the plugin, audits the EDA toolchain interactively, and optionally deploys global coding conventions.
# A1. Register the Marketplace (one-time)
/plugin marketplace add babyworm/rtl-agent-team
# A2. Install plugins (one-time)
/plugin install rtl-agent-team
/plugin install systemverilog-lsp # (optional) SV LSP
# A3. EDA toolchain audit (interactive interview — all steps are opt-in)
# - Q1 Required tools: python3, g++, make, verilator, cocotb, systemc
# + lint (verible AND/OR slang — at least one)
# + CDC (svlens OR sg_shell OR vc_cdc OR questa_cdc — at least one)
# — prompt to install missing ones (local/global/docker/skip)
# - Q2 Recommended/optional tools — user picks which to install:
# jq, yosys + sby, slang-server, iverilog, gtkwave
# - Q2b Commercial tool scan (vcs, xrun, dc_shell, sg_shell, vc_cdc, ...)
# — scan + collect env_source; not an install
# - Q2c Liberty file path for synthesis (optional)
# - Q3 Optional global deployment (yes/no) — deploys:
# ~/.claude/rules/rtl-coding-conventions.md
# ~/.claude/rules/rtl-verification-gate.md
# ~/.claude/CLAUDE.md diagram rule block (if tag missing)
/rtl-agent-team:rat-setup
If
systemverilog-lspis installed butslang-serveris missing, the sub-plugin checks onSessionStartand prompts forlocal(~/.local/bin, recommended),global, orskip.
Scaffolds project directory structure, deploys per-project rules and guides, and auto-installs EDA wrapper scripts. Run from inside the project directory. Existing templates and rules are left intact; managed exceptions are the RAT block in project CLAUDE.md, refreshed tool detection in rat_config.json, and regenerated config.mk. Usable tool path overrides are preserved, while stale or unusable paths are refreshed.
# B1. cd into your project directory
cd ~/work/my-rtl-project
# B2. Initialize project structure (run inside project)
# - Creates docs/, rtl/, sim/, refc/, lint/, syn/, formal/, reviews/
# - Deploys .claude/rules/ (coding conventions, verification gate)
# - Deploys subdirectory CLAUDE.md (phase-specific guides)
# - Auto-installs run_sim.sh, run_lint.sh, run_syn.sh, run_cdc.sh
# - Existing templates/rules are not overwritten; managed config is refreshed
/rtl-agent-team:rat-init-project
Execute RTL design and verification pipeline. Run from inside an initialized project — artifacts are created relative to CWD, so an uninitialized directory will not have the expected structure.
# C1. Full automation (6-Phase pipeline)
/rtl-agent-team:rat-auto-design
# Example natural-language usage:
# /rtl-agent-team:rat-auto-design "Design an H.264 TQ subsystem"
# /rtl-agent-team:rat-auto-design "implement VDC-M 1.2 encoder using reference C
# model in ../vdc-m/refc. Target 4K 60fps at 500MHz, margin 40% under TSMC 28nm"
AI-powered hardware development platform — design, verify, synthesize, and deploy working RTL with natural language. 18 agents, 25 skills, 8 IP blocks.
Xilinx full-toolchain assistant covering Vivado, Vitis HLS, Vitis Unified IDE, and PetaLinux -- from HLS algorithm to boot image
RTL-to-GDS-to-Graph skill collection. eda-install detects the machine and installs + verifies the open-source EDA toolchain (with a no-sudo conda path). signoff-loop drives an open-source EDA flow (Yosys + OpenROAD-flow-scripts + KLayout + Magic + Netgen + OpenRCX) from a spec or RTL to signed-off GDSII (DRC, LVS, RCX) with a self-improving fix/learn loop. def-graph converts the clean, signed-off physical design (DEF/LEF/SPEF) into PyTorch-Geometric graph datasets — five graph views (b–f), tech-lib/LEF parsing, and feature/label extraction. rtl-acquire discovers/screens RTL at corpus scale and expands it (synth-only) into pre-layout netlist graphs with dedup, quality scoring, and publish gating.
LTspice/ngspice circuit simulation with structured results — including per-device operating points (gm/gds/vth) read back by name, no rawfile parsing — plus LTspice .asc schematic editing, exposed as MCP tools. Tracks the latest ltspice-mcp release on PyPI.
JITX hardware design automation skills for PCB design, component modeling, substrate modeling, circuit creation, physical layout authoring, signal integrity constraints, pin assignment flexibility, code review, and mechanical CAD interchange.
Agentic KiCad PCB design workflow using SKiDL — architect, source, code, and verify circuits with AI agents.