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By babyworm
97-agent RTL design pipeline with 97 skills for 6-Phase hardware design automation (Research → Architecture → μArch → RTL → Verify → Design Note)
npx claudepluginhub babyworm/rtl-agent-team --plugin rtl-agent-teamBlock-level architecture designer for RTL projects — block diagrams, interfaces, data flow (Opus)
Full RTL design pipeline orchestrator. Manages 6-phase flow with dual-layer phase gates, parallel agent execution, feedback loops, and resumability. Spawns specialist agents for each phase and enforces quality gates between phases.
SystemC Bus Functional Model developer for TLM-2.0 AT non-blocking models with ARM AMBA protocol support (AXI/AHB/APB/ACE), payload pooling, and DPI-C co-simulation
CDC static analysis specialist. Detects clock domain crossings, verifies synchronizer presence, and analyzes RTL AST with slang for metastability risks.
CDC design strategy reviewer. Evaluates synchronization architecture quality, FIFO depth calculations, metastability budgets, and reset synchronization. Produces review reports in reviews/.
Policy rules, performance monitor naming conventions, BFM comparison thresholds (10% deviation), metric definitions, and verification checklists. Pure reference — no orchestration.
This skill should be used when the user asks to "measure RTL throughput", "verify performance against BFM baseline", "check latency vs BFM predictions", "performance verification for this module", "flag performance regression after RTL change", or when throughput and stall cycles must be validated as part of Phase 5 verification.
Policy rules, AXI/AHB/APB signal naming conventions, protocol assertion patterns, key protocol rules, and verification checklists. Pure reference — no orchestration.
Passive simulation tool profiles for replayable execution (verilator, iverilog, vcs, xrun, questa).
Passive synthesis tool profiles (yosys, dc_shell, genus) for replayable runs and comparable summary outputs.
Executes bash commands
Hook triggers when Bash tool is used
Modifies files
Hook triggers on file write and edit operations
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AI-powered hardware development platform — design, verify, synthesize, and deploy working RTL with natural language. 18 agents, 25 skills, 8 IP blocks.
RTL-to-GDS skill: drives an open-source EDA flow (Yosys + OpenROAD-flow-scripts + KLayout + Magic + Netgen + OpenRCX) from a natural-language spec or RTL to GDSII with DRC, LVS, and RCX signoff.
Xilinx full-toolchain assistant covering Vivado, Vitis HLS, Vitis Unified IDE, and PetaLinux -- from HLS algorithm to boot image
Agentic KiCad PCB design workflow using SKiDL — architect, source, code, and verify circuits with AI agents.
Hardware solution design skills and workflows for embedded and hardware engineers.
KiCad electronics design skills. Analyze schematics, review PCB layouts, download datasheets, source components, and prep boards for fabrication.
SystemVerilog/Verilog language server for Claude Code, powered by slang-server (hudson-trading). Provides diagnostics, hover, completion, go-to-definition, references, rename, and inlay hints for .sv/.svh/.v/.vh files.
Uses power tools
Uses Bash, Write, or Edit tools
Uses power tools
Uses Bash, Write, or Edit tools
Share bugs, ideas, or general feedback.
한국어 문서: README_kr.md
A Claude Code plugin for automated RTL design and verification. 99 specialized AI agents + 97 skills automate the 6-Phase pipeline: Research → Architecture → μArch → RTL → Verify → Design Note.
A Claude Code plugin for automated RTL design and verification.
Automates the 6-Phase design pipeline (Research → Architecture → μArch → RTL → Verify → Design Note) with 99 specialized AI agents + 97 skills + 11 reference documents.

This repository serves as the RTL Agent Marketplace, providing hardware design plugins.
| Plugin | Description | Version |
|---|---|---|
| rtl-agent-team | 99-agent RTL design pipeline (Research → Architecture → μArch → RTL → Verify → Design Note) | 0.11.4 |
| systemverilog-lsp | SystemVerilog/Verilog LSP (slang-server based — diagnostics, hover, go-to-definition, etc.) | 1.1.4 |
Additional plugins (domain knowledge packages, MCP servers, specialized skills, etc.) will be added to the Marketplace over time.
The workflow has three distinct stages, each with a different scope and frequency:
| Stage | Scope | Frequency | Commands |
|---|---|---|---|
| A. Machine Setup | Per machine (global) | Once per machine | /plugin install + /rtl-agent-team:rat-setup |
| B. Project Init | Per project directory | Once per project | /rtl-agent-team:rat-init-project |
| C. Design Work | Inside project | Recurring | /rtl-agent-team:rat-auto-design, phase/sub-skills |
Run each stage from its appropriate working directory: Stage A runs anywhere; Stages B and C should run from inside the target project directory (artifacts like docs/phase-*/, rtl/, .rat/state/ are written relative to CWD).
Installs the plugin, audits the EDA toolchain interactively, and optionally deploys global coding conventions.
# A1. Register the Marketplace (one-time)
/plugin marketplace add babyworm/rtl-agent-team
# A2. Install plugins (one-time)
/plugin install rtl-agent-team
/plugin install systemverilog-lsp # (optional) SV LSP
# A3. EDA toolchain audit (interactive interview — all steps are opt-in)
# - Q1 Required tools: python3, g++, make, verilator, cocotb, systemc
# + lint (verible AND/OR slang — at least one)
# + CDC (svlens OR sg_shell OR vc_cdc OR questa_cdc — at least one)
# — prompt to install missing ones (local/global/docker/skip)
# - Q2 Recommended/optional tools — user picks which to install:
# jq, yosys + sby, slang-server, iverilog, gtkwave
# - Q2b Commercial tool scan (vcs, xrun, dc_shell, sg_shell, vc_cdc, ...)
# — scan + collect env_source; not an install
# - Q2c Liberty file path for synthesis (optional)
# - Q3 Optional global deployment (yes/no) — deploys:
# ~/.claude/rules/rtl-coding-conventions.md
# ~/.claude/rules/rtl-verification-gate.md
# ~/.claude/CLAUDE.md diagram rule block (if tag missing)
/rtl-agent-team:rat-setup
If
systemverilog-lspis installed butslang-serveris missing, the sub-plugin checks onSessionStartand prompts forlocal(~/.local/bin, recommended),global, orskip.
Scaffolds project directory structure, deploys per-project rules and guides, auto-installs EDA wrapper scripts. Run from inside the project directory — non-destructive, so existing projects are safe (files are only created if missing).
# B1. cd into your project directory
cd ~/work/my-rtl-project
# B2. Initialize project structure (run inside project)
# - Creates docs/, rtl/, sim/, refc/, lint/, syn/, formal/, reviews/
# - Deploys .claude/rules/ (coding conventions, verification gate)
# - Deploys subdirectory CLAUDE.md (phase-specific guides)
# - Auto-installs run_sim.sh, run_lint.sh, run_syn.sh, run_cdc.sh
# - Non-destructive: never overwrites existing files
/rtl-agent-team:rat-init-project
Execute RTL design and verification pipeline. Run from inside an initialized project — artifacts are created relative to CWD, so an uninitialized directory will not have the expected structure.
# C1. Full automation (6-Phase pipeline)
/rtl-agent-team:rat-auto-design
# Example natural-language usage:
# /rtl-agent-team:rat-auto-design "Design an H.264 TQ subsystem"
# /rtl-agent-team:rat-auto-design "implement VDC-M 1.2 encoder using reference C
# model in ../vdc-m/refc. Target 4K 60fps at 500MHz, margin 40% under TSMC 28nm"