From rtl-agent-team
Generates SystemVerilog RTL wrapper modules instantiating third-party IP (memory, PLL, PHY, DSP) from IP-XACT descriptors or datasheets with project-convention port mapping, tie-offs, and linting.
npx claudepluginhub babyworm/rtl-agent-team --plugin rtl-agent-teamThis skill uses the workspace's default tool permissions.
<Purpose>
Generates design tokens/docs from CSS/Tailwind/styled-components codebases, audits visual consistency across 10 dimensions, detects AI slop in UI.
Records polished WebM UI demo videos of web apps using Playwright with cursor overlay, natural pacing, and three-phase scripting. Activates for demo, walkthrough, screen recording, or tutorial requests.
Delivers idiomatic Kotlin patterns for null safety, immutability, sealed classes, coroutines, Flows, extensions, DSL builders, and Gradle DSL. Use when writing, reviewing, refactoring, or designing Kotlin code.
<Use_When>
<Do_Not_Use_When>
<Why_This_Exists> IP instantiation is error-prone: wrong port widths, missing tie-offs, and parameter mismatches cause subtle bugs. Automated wrapper generation from the authoritative IP descriptor eliminates transcription errors and documents all connections explicitly. </Why_This_Exists>
<Execution_Policy>
skills/rtl-ip-instantiate/templates/ip-wrapper-template.sv as scaffoldi_ (input), o_ (output), io_ (bidirectional)clk (single domain) or {domain}_clk (multiple domains, e.g., sys_clk) — NOT clk_irst_n (single domain) or {domain}_rst_n (multiple domains, e.g., sys_rst_n) — NOT rst_nilogic only — no reg/wireu_ prefix (e.g., u_sram)gen_ prefix
</Execution_Policy><Tool_Usage>
Task(subagent_type="rtl-agent-team:rtl-explorer",
prompt="Read rtl/ip_wrappers/ and docs/ for existing wrapper patterns. Summarize: port naming convention (i_/o_/io_ prefixes), clock naming ({domain}_clk), reset naming ({domain}_rst_n), instance naming (u_ prefix).")
Task(subagent_type="rtl-agent-team:rtl-architect",
prompt="Read IP descriptor at docs/ip/{ip_name}.xml (or datasheet). List all ports, required tie-offs, and parameter settings. Design wrapper interface: map vendor port names to project convention (i_/o_/io_ prefixes, {domain}_clk, {domain}_rst_n).")
Task(subagent_type="rtl-agent-team:rtl-coder",
prompt="Write rtl/ip_wrappers/{ip_name}_wrapper.sv. Instantiate {ip_name} as u_{ip_name} with all ports connected per architect spec. Use logic only (no reg/wire). Port prefixes: i_ (input), o_ (output), io_ (bidirectional). Clock: sys_clk, reset: sys_rst_n. Follow CLAUDE.md coding conventions.")
</Tool_Usage>
rtl-explorer finds project uses AXI4-Lite for register interfaces with i_/o_ port prefixes; rtl-architect reads SRAM IP-XACT, maps 32 vendor ports to project convention (vendor clk→sys_clk, vendor rst_n→sys_rst_n, vendor din→i_sram_din); rtl-coder writes wrapper instantiating as u_sram with logic types only; rtl-lint-check passes. Writing wrapper without reading existing project conventions — creates inconsistent port naming that breaks downstream integration.<Escalation_And_Stop_Conditions>
<Final_Checklist>
// TIED: reason commentsi_/o_/io_ prefixes (NOT _i/_o suffix)clk or {domain}_clk naming (NOT clk_i)rst_n or {domain}_rst_n naming (NOT rst_ni)u_ prefix (e.g., u_{ip_name})logic types only — no reg/wire