vibe-ic

Codified after the v10627 / v10627-vendor false-PASS comparison. Inlined

Run the complete Vibe-IC flow (Phase 1 → Phase 2 → Analog → Phase 3) via vibe_ic_one_shot_runner. Auto-detects Path A vs B. AI-monitored + close-loop.

Run any known open IC-design benchmark (VerilogEval-v2/Human, RTLLM, CVDP, …) the CORRECT way per the open-benchmark-methodology skill. Auto-routes to the right run-shape (A/B/C/D), sets up the run dir scaffold, points at the blind instructions, and invokes the scorer. Use when "run benchmark X", "score benchmark X", "benchmark this", "reproduce X benchmark", "跑 benchmark", "重跑 RTLLM", "score VerilogEval".

Run Phase 1 (natural-language → L1-L27 JSON + human MD) via the deterministic phase1_one_shot_runner. AI-monitored + close-loop.

Run Phase 2 (L1-L27 → RTL → SOF → <half-duplex-tester> byte[6]=0xF2) via design_one_shot_runner. AI-monitored + close-loop ECO.

Runs Vibe-IC benchmark campaigns — "Run Benchmark Evaluation" (open benchmarks: VerilogEval / RTLLM / CVDP via /vibe-ic-benchmark) and "Benchmark IC" (the canonical ICs via /vibe-ic-all → /benchmark-verify). Commits + pushes results under benchmark-data/. When it finds a chip-AGNOSTIC plugin/MCP gap it AUTHORS the fix as a VERSION-LESS PR (owner directive 2026-06-21 "USE PR to issue bugs" — no backlog), which the repo-gatekeeper reviews + lands. The measure-only honesty is preserved by the NO-MIX gate: results and plugin fixes are NEVER in the same commit, so a hand-patch can never inflate a published number. Usable by maintainers (official numbers) and by end users locally.

The AUTHOR half (alias) of the single repo-gatekeeper maintainer role. Authors deterministic chip-AGNOSTIC fixes into the plugin/MCP, self-verifies (reproduce + the cadence-correct suite the CI way), and ships them by DIRECT PUSH (2026-06-26 owner directive — direct commit + `git push origin main`, no PR ceremony; the pusher assigns the monotonic version pre-push and every gate is retained). Runs the `core-agent-loop` procedure. See `vibe-ic:repo-gatekeeper`.

The general-usage audit role. Runs the plugin against real benchmark IC projects, finds systematic chip-AGNOSTIC quality gaps, and files them as ORGANIC backlog issues for the Core Agent — then audits the closed fixes on real silicon and reopens any that are inadequate. Files backlog only; never checks in to benchmark-data, the plugin, or the MCP. Runs the `field-agent-loop` procedure.

The LAND half (alias) of the single repo-gatekeeper maintainer role — the sole merger of PRs and the assigner of versions at merge. It also authors (via the core-agent-loop half); there is NO author≠approver requirement. Quality is guaranteed by the GATES (machine checks + Step-2.7 adversarial §4.05 review + the serialized re-test-on-rebase merge queue), not by identity separation. Runs the gatekeeper-loop: for every PR it enforces the doctrine constraints (GENERAL / no-cheat / chip-AGNOSTIC / §4.05 no-leak), assigns the next monotonic version, and squash-merges. Never --admin/--force/--no-verify. See `vibe-ic:repo-gatekeeper`.

Append-only chronological record of lessons filed into `ic_expert_db.json` via

Plan and run analog / mixed-signal simulations — DC op, AC, transient, Monte Carlo, corner sweeps, PSRR/CMRR, noise — using ngspice, Xyce, Spectre, or HSPICE, and triage the results. Use when the user says "SPICE", "ngspice", "Monte Carlo", "corner simulation", "analog sim", "AC analysis", "transient", "PSRR", "CMRR", "noise analysis".

Post-layout parasitic extraction + re-simulation for analog blocks — compares pre-layout vs post-layout specs. Use when the user says "post-layout resim", "extract and resimulate", "parasitic check", or at Step A7 of the analog track.

Canonical reference doc for the Analog A1-A9 track — spec extraction → topology → netlist → corner sweep → layout → per-block PV (DRC/LVS) → post-layout resim → hardmacro → HIL. Used when an agent wants to walk the A1-A9 plan step-by-step. For unified one-command execution (deterministic runner + AI fall-through + final audit aggregated), prefer the slash command `/vibe-ic-analog` (v1.6.13+) which merges this skill's workflow with `analog_one_shot_runner.py`.

Package a verified analog block into a hardmacro (LEF abstract + Liberty timing + GDS + behavioral Verilog) for digital PnR integration. Use when the user says "package analog block", "generate hardmacro", "create LEF/Liberty", or at Step A7 of the analog track.

Execute hardware measurements on analog blocks via scope capture + FPGA ADC read. Use when running hardware-in-the-loop verification, "measure analog", "scope capture", "read ADC", or during analog hardware tuning.

4 hooks across 2 events