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From rtl-agent-team
Generates Markdown documentation for SystemVerilog RTL modules — port tables, parameter tables, instance trees, FSM sections, and synthesis summaries. Auto-extracts structure from SV source to keep docs accurate.
npx claudepluginhub babyworm/rtl-agent-team --plugin rtl-agent-teamHow this skill is triggered — by the user, by Claude, or both
Slash command
/rtl-agent-team:rtl-document [module-name | --all][module-name | --all]This skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
<Purpose>
Maps and documents SystemVerilog codebases, generating module hierarchies, signal flows, clock domains, FSM diagrams, and RTL architecture overviews.
Generates IEEE 1685-2014 IP-XACT XML descriptors from SystemVerilog RTL sources. Use for EDA tool integration (Vivado, Quartus, Genus) or automated SoC port connection.
Generates engineering documentation from KiCad projects—HDDs, CE Technical Files, ICDs, design reviews, and manufacturing packages. Auto-runs analyses, renders SVGs, generates block diagrams, and produces PDFs.
Share bugs, ideas, or general feedback.
<Use_When>
<Do_Not_Use_When>
<Why_This_Exists> RTL documentation written by hand drifts from implementation. Auto-extraction from SV source keeps port tables, parameter lists, and instance trees accurate. The skill splits work between a deterministic parser (objective structure) and the LLM (functional description, FSM semantics, design rationale), making the contract surface explicit and regression-debuggable. </Why_This_Exists>
rtl/**/*.sv.syn/synth_report.txt for area/timing summary.If the prerequisite is missing: WARNING — recommend running /rtl-agent-team:rtl-p4-implement first. Proceed with available artifacts; the orchestrator adapts scope.
<Responsibility_Boundary>
<!-- LLM_FILL: ... --> markers in rendered output mark the contract surface. Replace each marker; never delete.
</Responsibility_Boundary>Apply steps 1-6 to every requested module. When --all is passed, fan out using one task per module in parallel.
<Tool_Usage> Manual-extraction fallback (when verible is unavailable):
Task(subagent_type="rtl-agent-team:rtl-explorer",
prompt="Document RTL module per skills/rtl-document/. Read rtl/{module}/{module}.sv, extract ports/parameters/instances/FSM, apply project naming conventions, and fill the LLM_FILL markers in docs/rtl/{module}.md.")
Synthesis summary:
Task(subagent_type="rtl-agent-team:synthesis-reporter",
prompt="Summarize syn/synth_report.txt and syn/timing_report.txt for the docs/rtl/{module}.md synthesis section.")
</Tool_Usage>
Small datapath module, no FSM, single clock domain. skills/rtl-document/examples/simple_fifo.md Port table only; FSM and D2 sections omitted by render_doc.py because the JSON has empty fsm_candidates and one instance or fewer. AXI-Stream bridge with two clock domains. skills/rtl-document/examples/axi_stream_bridge.md Ports grouped by AXI / APB; Clock Domains table lists both `sys` and `pixel`; D2 block diagram shows the async-FIFO bridge. FSM-heavy codec module with multiple sub-instances. skills/rtl-document/examples/cabac_encoder_excerpt.md FSM table with Mermaid `stateDiagram-v2`; D2 block diagram for the sub-instance tree; functional description references the relevant standard section.<Escalation_And_Stop_Conditions>
extract_module_doc.py returns SV parse error → report file:line; do not fabricate ports. Ask the user to fix the syntax first.fsm_candidates: []. Add an FSM section manually only when a state machine clearly exists and the state register is identifiable.data_i suffix) → record in convention_violations and surface the violation at the top of the generated doc. Do not rewrite the RTL.
</Escalation_And_Stop_Conditions>docs/rtl/{module}.md — per-module documentation./tmp/{module}.json — intermediate extraction (transient; not committed).<Final_Checklist>
docs/rtl/{module}.md exists for every requested module.i_/o_/io_ prefix; clock/reset rows tagged kind=clock|reset.UPPER_SNAKE_CASE.u_ prefix.<!-- LLM_FILL: ... --> markers replaced.syn/synth_report.txt exists.