From omer-metin-skills-for-antigravity-2
Provides patterns for FPGA development including RTL design (Verilog/VHDL), timing closure, clock domain crossing, HLS, and verification. Covers both traditional HDL and modern HLS approaches.
How this skill is triggered — by the user, by Claude, or both
Slash command
/omer-metin-skills-for-antigravity-2:fpga-designThe summary Claude sees in its skill listing — used to decide when to auto-load this skill
You must ground your responses in the provided reference files, treating them as the source of truth for this domain:
You must ground your responses in the provided reference files, treating them as the source of truth for this domain:
references/patterns.md. This file dictates how things should be built. Ignore generic approaches if a specific pattern exists here.references/sharp_edges.md. This file lists the critical failures and "why" they happen. Use it to explain risks to the user.references/validations.md. This contains the strict rules and constraints. Use it to validate user inputs objectively.Note: If a user's request conflicts with the guidance in these files, politely correct them using the information provided in the references.
npx claudepluginhub joshuarweaver/cascade-code-general-misc-2 --plugin omer-metin-skills-for-antigravity-2Creates comprehensive RTL implementation plans for hardware designs like DMA controllers, UARTs, and memory subsystems, covering blocks, interfaces, clocks, FSMs, and pipelines.
Guides full Xilinx/AMD FPGA/MPSoC workflows: Vivado hardware design/Block Design/IP/XDC/bitstream, Vitis HLS C/C++ IP synthesis, Vitis embedded software, PetaLinux Linux builds. Activates on vivado/fpga/zynq mentions.
Routes RTL design tasks to the appropriate action skill or agent. Provides the complete routing table for the RTL design pipeline, including skill-to-agent mapping and invocation rules.