From skidl-skills
Creates or resumes a PCB circuit design through an interview-to-export pipeline. Reads project state and spawns an orchestrator for architecture, part sourcing, SKiDL coding, ERC, and export.
How this skill is triggered — by the user, by Claude, or both
Slash command
/skidl-skills:new-circuitThe summary Claude sees in its skill listing — used to decide when to auto-load this skill
- User asks to start, create, or design a new circuit
/skidl-ee:new-circuitpipeline_state.json (project root, see schema in pipeline_state_schema.json).stage is not "initial", ask: "Resume current circuit <circuit_name> or start fresh?"orchestrator agent and pass:
pipeline_state.json contentspipeline_state.json — existing state (may be absent on first run)pipeline_state.json with completed stages and file pathsSPEC.md, circuits/*.py, outputs/*.net, outputs/BOM.csvnpx claudepluginhub nickkraakman/skidl-skills --plugin skidl-skillsAutomates KiCad to EasyEDA to JLCPCB PCB workflow: project setup, LCSC part sourcing, pin-map fetching, fully-wired .kicad_pcb generation via pcbnew, and EasyEDA handoff for routing and ordering.
Guides EasyEDA Pro workflows via EasyEDA MCP Pro: server setup, schematic/PCB inspection, controlled writes, exports, BOM/DRC/ERC, and status reporting.
Orchestrates KiCad EDA via kicad-mcp MCP server for schematic creation, PCB layout, autorouting, DRC, and Gerber export. Enforces serialized PCB ops and library-first lookup.