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From skidl-skills
Creates or resumes a PCB circuit design through an interview-to-export pipeline. Reads project state and spawns an orchestrator for architecture, part sourcing, SKiDL coding, ERC, and export.
npx claudepluginhub nickkraakman/skidl-skills --plugin skidl-skillsHow this skill is triggered — by the user, by Claude, or both
Slash command
/skidl-skills:new-circuitThe summary Claude sees in its skill listing — used to decide when to auto-load this skill
- User asks to start, create, or design a new circuit
Automates KiCad to EasyEDA to JLCPCB PCB workflow: project setup, LCSC part sourcing, pin-map fetching, fully-wired .kicad_pcb generation via pcbnew, and EasyEDA handoff for routing and ordering.
Generates KiCad schematics and PCBs from natural language prompts with DRC/ERC checks and AI verification loop. Outputs project files, BOM, and report. Ideal for prototyping boards like iCE40 breakouts.
Edits and creates KiCad 6+ schematic (.kicad_sch) files: modify values, add/remove components, update connections, and generate schematic content from specs or ASCII diagrams.
Share bugs, ideas, or general feedback.
/skidl-ee:new-circuitpipeline_state.json (project root, see schema in pipeline_state_schema.json).stage is not "initial", ask: "Resume current circuit <circuit_name> or start fresh?"orchestrator agent and pass:
pipeline_state.json contentspipeline_state.json — existing state (may be absent on first run)pipeline_state.json with completed stages and file pathsSPEC.md, circuits/*.py, outputs/*.net, outputs/BOM.csv