From chipdev-method
Guides RTL frontend design discipline — module boundary rules, synthesizability constraints, observability instrumentation, lint cleanliness as a hard gate, reset strategy, and clock-domain crossing. Activate when the user explicitly invokes /chipdev-method:build-rtl, or asks "RTL 怎么分层", "should I use always_ff or always", "怎么做 lint clean", "reset strategy", "CDC how to handle", or starts writing SystemVerilog for a new module.
npx claudepluginhub curryfromuestc/dev-guide --plugin chipdev-methodThis skill uses the workspace's default tool permissions.
Use this skill when the user is writing SystemVerilog (or another HDL) for
Monitors deployed URLs for regressions after deploys, merges, or upgrades by checking HTTP status, console errors, network failures, performance (LCP/CLS/INP), content, and API health.
Share bugs, ideas, or general feedback.
Use this skill when the user is writing SystemVerilog (or another HDL) for a chip frontend module. Do not autoload.
The point of this skill is to give the user a small set of non-negotiable disciplines — module boundary rules, synthesizability constraints, lint cleanliness, observability hooks. These disciplines pay back as the design scales. Letting any of them slip in Phase 0–1 creates a debt that is order-of-magnitude more expensive to repay in Phase 4.
When triggered:
define-contracts first — interfaces and hierarchy should
come from the same DSL the simulator uses.[abstract]Five rules. Every rule has a long-term cost when violated.
cmd_in, cmd_out, data_resp_out are unambiguous. cmd is not.proc_* callbacks) trivially safe.valid + ready for any port pair where the receiver has bounded
capacity. Decide protocol with the contract, not at integration time.If the project uses an interface DSL (see define-contracts), rules
2, 3, 4 are largely enforced by the generator.
[abstract]Hard rules. Never violate in synthesizable RTL.
always_ff with an explicit clock and
optional reset.always_comb (which auto-detects
sensitivity).always @(*) — use always_comb. The latter catches latch
bugs at elaboration.real, time, realtime in synthesizable code.$display, $write, $fopen, $fclose in synthesizable
scopes (they're fine inside if (!synthesis) debug blocks if your
tools support it).wait, force, release outside testbenches.@(...), wait(...) inside
function).These should be enforced by lint as a hard gate (see "Lint clean as a hard gate" below).
[industry-pattern]logic instead of wire/reg.always_ff / always_comb / always_latch.unique case / priority case when the intent is documented.parameter and (for elaboration-time) localparam.wire reg style mixed declarations.assign for anything beyond simple wire connections.{32'h0, foo}, not foo extended silently).if-chains are not.PascalCase or snake_case, pick one project-wide.snake_case. Direction-suffixed (_in, _out).UPPER_SNAKE.UpperCamel or UPPER_SNAKE, pick one.These are conventions. The point of conventions is that they are uniform. Less important which you choose, more important that you choose one.
[abstract]RTL must be observable to the difftest infrastructure (see
align-and-difftest). Plan instrumentation at module write time, not
afterwards.
For every architectural state element this module owns (a register, an output of a state machine that implements an architectural commit), expose a probe interface:
// At commit time, push the architectural value out to the difftest probe.
`ifdef DIFFTEST
always_ff @(posedge clk) begin
if (commit_valid) begin
$diff_commit_register(reg_id, reg_data);
end
end
`endif
Wrap probes in ifdef DIFFTEST so synthesis sees nothing. The DPI-C
function $diff_commit_register (or whatever name the project uses) is
defined by the difftest framework.
valid cannot drop without ready having been asserted).assert property) so the same property runs in simulation
and formal.These are not optional in a project targeting tape-out. Plan to write them as you write the module, not afterwards.
[industry-pattern]Three workable strategies. Pick one project-wide.
| Strategy | Pros | Cons | When to choose |
|---|---|---|---|
Synchronous active-low (if (!rst_n) ...) | Cleanest in flop libraries; simulator-friendly. | Needs reset to be deterministically sampled. | Default for most digital frontends. |
| Asynchronous assert, sync de-assert | Tolerates reset outside clock domain. | Requires careful CDC on reset. | Mixed clock domains, many resets. |
| Asynchronous active-high | Common in some legacy flows. | Synthesis quality varies; sim-RTL gap risk. | Only when forced by foundry / library. |
Document the choice once at project root, enforce in lint.
A separate concern: don't reset what doesn't need it. Datapath flops (pipeline registers, FIFO entries) usually don't need reset; control flops (state, enables, valid) almost always do. Resetting datapath flops increases area and sometimes timing.
[abstract]CDC bugs are silent in simulation and lethal in silicon. Three rules:
If the project will have only one clock domain, this section is optional — but get the policy down even before adding a second domain.
[abstract]This is the single highest-leverage discipline in RTL development. The project should treat lint warnings as build failures from day one. Retrofitting lint cleanliness in Phase 4 takes weeks; maintaining it from Phase 0 takes minutes per module.
Enable at minimum:
always_comb without complete assignments).always_ff.Tools: Verilator's --lint-only for free baseline; SpyGlass /
VC-SpyGlass / AscentLint / SLang for production-grade.
If the project is already past Phase 1 without lint:
[abstract]always and always_ff — synthesis treats them differently,
simulation may not. Pick always_ff everywhere for sequential.default in case — synthesizes a latch silently. Always
use unique case with a default branch.choose-artifact — when RTL is the right next step.define-contracts — the interface and hierarchy DSL the RTL consumes.align-and-difftest — how the RTL serves as the DUT for difftest.references/lint-rule-set.md — long-form lint policy.references/case-ibex.md — lowRISC Ibex SV style.references/case-boom.md — BOOM processor design.references/case-xiangshan-coding-style.md — Chisel idioms transferable
to SV.