Formal property verification and model checking skill for FPGA designs
Performs exhaustive formal verification and model checking for FPGA design properties using SVA assertions.
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README.mdExpert skill for formal property verification and model checking, enabling exhaustive verification of FPGA design properties without simulation.
// Safety property
assert property (@(posedge clk) disable iff (rst)
req |-> ##[1:5] gnt);
// Liveness property (bounded)
assert property (@(posedge clk) disable iff (rst)
req |-> s_eventually gnt);
// Assumption for formal
assume property (@(posedge clk)
$onehot0(req_vec));
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